library verilog;
use verilog.vl_types.all;
entity PIECoder is
    generic(
        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
        SOF             : vl_logic_vector(0 to 1) := (Hi0, Hi1);
        BYTE            : vl_logic_vector(0 to 1) := (Hi1, Hi0);
        EOF             : vl_logic_vector(0 to 1) := (Hi1, Hi1)
    );
    port(
        Clk             : in     vl_logic;
        Rst             : in     vl_logic;
        Din             : in     vl_logic_vector(7 downto 0);
        Le              : in     vl_logic;
        N               : in     vl_logic_vector(3 downto 0);
        Dout            : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of IDLE : constant is 1;
    attribute mti_svvh_generic_type of SOF : constant is 1;
    attribute mti_svvh_generic_type of BYTE : constant is 1;
    attribute mti_svvh_generic_type of EOF : constant is 1;
end PIECoder;
